A CMOS image sensor with in-pixel ADC, timestamp, and sparse readout

Abstract:: Recent developments in CMOS image sensors have focused on the advancement of digital pixel sensors (DPS). A novel DPS aiming to combine multiple functionalities on the imaging plane has been designed and tested: The on pixel intelligent CMOS (OPIC) sensor was manufactured in a 0.25 mum logic process with 5 metal layers, and 8 mum epitaxial layers. The sensor comprises three 2 ,times,2 mm test arrays of 30 mum pixels. Two of the test arrays are named advanced and include two 8-bit DRAM cells, one 8-bit ROM cell, and one 1-bit DRAM cell per pixel. The 8-bit DRAM cells can record both ADC and time-to-threshold data, while the ROM hard codes the pixel address within the array. The 1-bit DRAM acts as a hit flag enabling automatic sparsification of the image data based on an external threshold. © 2006 IEEE.

Authors:: JP Crooks, SE Bohndiek, CD Arvanitis, R Speller, H Xingliang, EG Villani, M Towrie, R Turchetta

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